MOSFET (metal-oxide-semiconductor field effect transistor) devices have many industrial applications, such as power amplifiers, power switches, low noise amplifiers and digital Integrated Circuits (IC) to name a few. As a fundamental building cell for a great variety of electronic products, the practitioners in the art of MOSFET device design and fabrication are constantly improving its performance parameters such as power efficiency, maximum operating voltage, integration density and frequency response, to name a few.
In U.S. Pat. No. 5,406,110 by Kwon, et al., a lateral double diffused insulated gate field effect transistor (LDMOS) with reduced surface field (RESURF) was described and illustrated in FIG. 1. Here, a transistor (10) has a thin epitaxial layer (14) of a second conductivity type on a semiconductor substrate (12) of a first conductivity type. A drift region (24) of the second conductivity type is formed extending through the thin epitaxial layer (14) to the substrate (12). A thick insulator layer (26) is formed on the drift region (24). An IGFET body (28) of the first conductivity type is formed adjacent the drift region (24). A source region (34) of the second conductivity type is formed within the IGFET body (28) and spaced from the drift region (24) defining a channel region (40) within the IGFET body (28). A conductive gate (32) is insulatively disposed over the IGFET body (28) and extends from the source region (34) to the thick insulator layer (26). A drain region (36) is formed adjacent the drift region (24). In the art, the conducting channel of an LDMOS device is formed laterally. Usually the source, drain and gate are located on the surface of the wafer. With the above device structure and its associated fabrication method involving a lateral double diffusion process, U.S. Pat. No. 5,406,110 described numerous technical advantages over its prior transistors and fabrication processes in the art. One technical advantage was the ability to diffuse the IGFET body (28) and still have a drift region (24) with a high doping concentration. Another technical advantage was the ability to vary the breakdown voltage rating of the output devices by simply adjusting the implant dose. Another technical advantage was the ability to fabricate multiple transistors with different breakdown voltage ratings on the same chip through proper masking of different drift region implants. Yet another technical advantage was the reduction in the on-resistance over conventional transistors while maintaining the same breakdown voltage rating. Still another technical advantage was to provide a current path between the drift region (24) and the channel region (40) necessary to avoid increasing the on-resistance of the device.
In U.S. Pat. No. 5,517,046 by Hsing, et al., a high voltage lateral DMOS (LDMOS) device with enhanced drift region was described and illustrated in FIG. 2. An LDMOS transistor structure formed in N-type silicon is disclosed which incorporates a special N-type enhanced drift region (61). In one embodiment, a cellular transistor with a polysilicon gate mesh is formed over an N epitaxial layer (52) with P body regions (59), P.sup.+ body contact regions (58), N.sup.+ source (62) and drain regions (64), and N enhanced drift regions (61), etc. The N enhanced drift regions (61, etc.) are more highly doped than the epitaxial layer (52) and extend between the drain regions and the gate (56) (with gate oxide 54). Metal strips (67, 68) are used to contact the rows of source (62) and drain (64) regions. The N enhanced drift regions (61) serve to significantly reduce on-resistance without significantly reducing breakdown voltage.
Regarding both U.S. Pat. No. 5,406,110 and U.S. Pat. No. 5,517,046, while the technique of lateral double diffusion with a differential dopant profile can create high voltage LDMOS devices with the following advantages:                No extra mask is needed, and        Device channel can be made very short and is self-aligned to the gate,the double diffusion process requires high temperature plus long diffusion time to drive dopants into the body region and is thus undesirable as it affects the wafer property. More specifically, using double lateral diffusion to create short-channel requires a high temperature around 1100 deg C. and long drive-in time of the order of an hour, as opposed to an LVCMOS (low voltage CMOS) process with temperature less than 950 deg C. As a result, the double diffusion process causes certain undesirable material property changes from the LVCMOS process. In the art, the associated limitation on diffusion temperature and time is called thermal budget. Additionally, without adding an extra polysilicon layer, the LDMOS process is not compatible with a popular industry standard sub-micron CMOS process.        
In the following prior art paper:
Title: Complementary LDMOS transistors for a CMOS/BiCMOS process
Authors: S. Whiston, D. Bain, A. Deignan, J. Pollard, C. Ni Chleirigh, C. Musgrave, M. O'Neill Analog Devices, Raheen Industrial Estate, Limerick, Ireland Publication:
Power Semiconductor Devices and ICs, 2000. Proceedings. The 12th International Symposium on Semiconductor Devices, pages 51-54
Publication Date: 2000
Meeting Date May 22, 2000-May 25, 2000
Location: Toulouse, France
ISBN: 0-7803-6269-1
INSPEC Accession Number: 6734962
Digital Object Identifier: 10.1109/ISPSD.2000.856771
as illustrated in FIG. 3A and FIG. 3B, a method of using multiple implants that are self-aligned to the poly gate edge to form an LDMOS is described. This method allows implementation of complementary LDMOS devices onto existing CMOS/BiCMOS processes without the addition of any thermal treatments thereby having no effect on the existing CMOS/BiCMOS device performance. This approach gives greater flexibility in controlling the body doping profile in the lateral and vertical directions enabling threshold voltage (Vt) and breakdown voltage (BV) optimization for a wide range of source junctions that exist in many intrinsic and foundry processes. It is observed that Whiston et al used large angle tilt implant (LATID), where the implant tilt angle can be up to 45 degrees, to define the short channel body. It is further pointed out that the LATID does have the following disadvantages:                Need refractory metal to stop excessive penetration of body implant through the gate        Sensitivity of channel length to thickness variations of the gate stack        Shadowing effects from source window opening causing undesirable deviation of the body implant profile        Low ruggedness of device due to constraints on body implant dose for threshold voltage control        
Hence, further improvements are desirable to make ultra short channel lateral MOSFETs with correspondingly reduced on-resistance without using either the double diffusion process or the large angle tilt implant (LATID).